A semiconductor component with charge compensation structure is disclosed in the document DE 101 32 136 C1. Such charge compensation structures form the basis of COOLMOS® (registered trademark DE 38844786.5) semiconductor power devices. In the case of such semiconductor power devices with the charge compensation structure, p-type and n-type zones below the actual MOS field-effect transistor structure with source and gate zones, and also below the associated MOS channels are arranged next to one another in the semiconductor volume of the semiconductor power chip or interleaved in one another in such a way that, in the off-state case, their charges can be mutually depleted and that, in the activated state, there results an uninterrupted, low-impedance conduction path from a source electrode near the surface to a drain electrode arranged on the rear side.
The compensation principle is based on a mutual compensation of charges in n- and p-doped zones in the drift region of the vertical MOS transistor. In this case, the zones are spatially arranged such that the path integral over the doping along for example a line running vertically with respect to the pn junction in each case remains below the material-specific breakdown voltage. For this purpose, p-type and n-type pillars or plates or compensation zones may be arranged pairwise in a vertical transistor as is used in power electronics.
By virtue of the extensive compensation of the p-type and n-type dopings, the doping of the current-carrying region can be significantly increased in the case of compensation components which results in a significant reduction of the on-state resistance despite the loss of a current-carrying area. The reduction of the on-state resistance of such semiconductor power devices is associated with a reduction of the heat loss, so that such semiconductor power devices with charge compensation structure remain “cool” compared with conventional semiconductor power devices.
On account of the pillar structure of the charge compensation cells that extend over the entire top side and the volume of the semiconductor chip of the semiconductor power device the problem arises of arranging signal-processing and/or controlling, integrated circuits monolithically on the semiconductor chip of the semiconductor power device. A further problem consists in isolating the region of the semiconductor circuit elements for the integrated circuit from the region of the semiconductor power elements, especially as the drift zone is relatively highly doped in the semiconductor chip with COOLMOS® semiconductor power devices. With the introduction of a deep p-type well, for example for n-MOS transistors or CMOS structures of a monolithic integrated circuit, this leads to a reduction of the breakdown voltage for the semiconductor power device.